The waveform of a digital signal outputted from a transmitter degrades while being transmitted from the transmitter to a receiver via a transmission channel, requiring that the clock signal and data be recovered at the receiver. Clock/data recovery devices for carrying out this kind of recovery, for example, are disclosed in Patent Documents 1, 2.
The devices disclosed in these documents take into account the fact that data transition times fluctuate in the waveform-degraded digital signal, and detect each bit of data at three timings. Of the three timings when each bit of data is detected at this time, a first timing is set in proximity to the start time of the data stability period of the pertinent bit, a second timing is set in proximity to the end time of the data stability period of the pertinent bit, and a third timing is set at a middle time between the first timing and the second timing.
Then, the device disclosed in Patent Document 1 recovers the clock signal by adjusting the respective timings such that all the data detected at the three timings for each bit matches, and recovers the data at this time by detecting the data of each bit at the middle third timing.
Conversely, the device disclosed in Patent Document 2 recovers the clock signal by adjusting each timing such that the bit error rates for each of the first timing and the second timing (that is, rates at which the data detected at each of these timings differs from the data detected at the middle third timing) are equivalent to one another, and, in addition, lie within the start setting range, and recovers data by detecting the data of each bit at this time at the middle third timing.
[Patent Document 1] Japanese Patent Application Laid-open No. H7-221800
[Patent Document 2] National Publication of Translated Version No. 2004-507963